The general principle of connecting or coupling devices together using for example a control bus for selecting some element within the remote device and data bus for providing or retrieving information concerning the element within the remote device are generally known. For example systems containing one master device and one slave device and where the master device communicates with the slave device and the slave device performs data transactions as per a predefined protocol are generally known and implemented widely.
However such single master single slave communication couplings typically fail where additional devices use the same bus or, link, or coupling. In such systems where there is more than one slave device typically a device address bus is implemented to select one of the devices. For example a typical example is shown in FIG. 1 where a master device (port) 1 can be coupled to a first device ‘Device 1’ 101 and a second device ‘Device 2’ 102 via a main clock coupling (MAIN CLOCK) 3, a control signal coupling (CTRL_SIG_OUT) 5 and a data signal coupling (DATA_OUT) 7. The master device 1 in order to select one of the devices to communicate with is further coupled to an address logic decoder (Logic) 9 using a dedicated select address coupling 15 on which dedicated select signals can be sent. The address logic decoder 9 can furthermore be coupled to each of the devices via additional dedicated selection couplings (such as shown in FIG. 1 by the first dedicated select coupling 16 between the logic 9 and the first device 101 and the second dedicated select coupling 17 between the logic 9 and the second device 102.
As dedicated lines or couplings are required for each device this can limit expansion in the design. In other words it is not possible to increase the number of slave devices in the system beyond the number of dedicated couplings between the address logic decoder and device. Furthermore such approaches require additional coupling lines between the master device, address decoding device and the slave devices as well as a specific address decoding logic apparatus.